Please use this identifier to cite or link to this item: http://hdl.handle.net/11400/10162
Title: Modified self-organizing feature map algorithms for efficient digital hardware implementation
Authors: Βασιλάς, Νικόλαος
Thiran, P.
Ienne, P.
Item type: Journal article
Keywords: Αυτο-οργανωμένοι χάρτες;Αλγόριθμοι;ψηφιακή εφαρμογή υλικού;διανύσματα εισόδου;Self-organizing maps;GMDH algorithms;digital hardware implementation;input vectors
Subjects: Πληροφορική
Μηχανική υπολογιστών
Computer science
Computer engineering
Issue Date: 11-May-2015
Mar-1997
Abstract: This paper describes two variants of the Kohonen's self-organizing feature map (SOFM) algorithm. Both variants update the weights only after presentation of a group of input vectors. In contrast, in the original algorithm the weights are updated after presentation of every input vector. The main advantage of these variants is to make available a finer grain of parallelism, for implementation on machines with a very large number of processors, without compromising the desired properties of the algorithm. In this work it is proved that, for one-dimensional (1-D) maps and 1-D continuous input and weight spaces, the strictly increasing or decreasing weight configuration forms an absorbing class in both variants, exactly as in the original algorithm. Ordering of the maps and convergence to asymptotic values are also proved, again confirming the theoretical results obtained for the original algorithm. Simulations of a real-world application using two-dimensional (2-D) maps on 12-D speech data are presented to back up the theoretical results and show that the performance of one of the variants is in all respects almost as good as the original algorithm. Finally, the practical utility of the finer parallelism made available is confirmed by the description of a massively parallel hardware system that makes effective use of the best variant.
Description: σε έντυπη μορφή στο γραφείο μου
Language: English
Citation: Vassilas, N., Thiran, P. and Ienne, P. (1997) Modified self-organizing feature map algorithms for efficient digital hardware implementation. IEEE Transactions on Neural Networks. [Online] 8 (2), pp.315-330. Available from: http://ieeexplore.ieee.org [Accessed 11/05/2015]
Journal: IEEE Transactions on Neural Networks
Type of Journal: With a review process (peer review)
Access scheme: Embargo
License: Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες
URI: http://hdl.handle.net/11400/10162
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