Please use this identifier to cite or link to this item: http://hdl.handle.net/11400/10591
Title: Modelling MOSFET gate length variability for future technology nodes
Authors: Πάτσης, Γεώργιος
Item type: Journal article
Keywords: Microelectronics;Chip;Technology nodes;Τεχνολογικοί κόμβοι;Μικροηλεκτρονική;Ολοκληρωμένο σύστημα
Subjects: Technology
Electronics
Τεχνολογία
Ηλεκτρονική
Issue Date: 17-May-2015
17-Sep-2008
Publisher: Wiley
Abstract: Gate length variability due to intra or inter die variations can lead to considerable mismatch between devices even inside the same chip. This variability has to be considered in detail and new device models should be developed, aiming in modelling its effects on the electrical characteristics devices. In this work the Philips MM11 MOSFET model is extended to incorporate gate length variability. This is introduced by dividing the device width into sub-units following a Gaussian gate length distribution, with appropriate line-width roughness. The combined model is used to quantify the drain-source current in terms of gate line-width roughness. The model is coded in VHDL-AMS in order to be used for simulation of circuit behaviour inside the framework of appropriate system simulation software such as Ansfoft's Simplorer.
Language: English
Citation: Patsis, G. (2008) Modelling MOSFET gate length variability for future technology nodes. "Physica status solidi", 205 (11), p.2541–2543
Journal: Physica status solidi
Type of Journal: With a review process (peer review)
Access scheme: Embargo
License: Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες
URI: http://hdl.handle.net/11400/10591
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