Please use this identifier to cite or link to this item: http://hdl.handle.net/11400/6069
Title: Implementation of 90 nm CMOS LFSR test vector generator for FPGA floating point arithmetic unit
Authors: Noorbasha, Fazal
Madhav, Venu C. S.
Hu, Jacqueline
Harsha Vardhan, GSRK Reddy
Rolla, Sireesha
Contributors: Joshi Ram Charan Tej, P.
Item type: Conference publication
Keywords: FPAU;IEEE 754;Sticky bit;Round bit;Guard Bit;LFSR;High speed computing;Υπολογιστική υψηλής ταχύτητας
Subjects: Science
Physics
Επιστήμες
Φυσική
Issue Date: 11-Feb-2015
2013
Date of availability: 11-Feb-2015
Publisher: Νερατζής, Ηλίας
Σιανούδης, Ιωάννης
Abstract: In this paper, we present the LFSR Test Vector Generator for Floating Point Arithmetic Unit (FPAU); it improves the performance of multimedia processing with low hardware cost. Here, we focused on a decimal floating point unit which consists of adder and subtractor for high speed computing. It takes input as binary real numbers, converts them into single precision IEEE 754 format floating point numbers, performs operations and gives the output with high precision. We used Guard bit, Sticky bit and Round bit to get output with good precision. At last, we tested the unit by the values from LFSR. The FPAU was modeled and synthesized in Verilog HDL and LFSR was implemented 90nm CMOS technology.
Language: English
Citation: Noorbasha, F., Madhav, V.C.S., Hu, J., Harsha Vardhan, GSRK R., Rolla, S., et al. (2013). Implementation of 90 nm CMOS LFSR test vector generator for FPGA floating point arithmetic unit. "e-Journal of Science & Technology". [Online] 8(3): 85-93. Available from: http://e-jst.teiath.gr/
Journal: e-Περιοδικό Επιστήμης & Τεχνολογίας
e-Journal of Science & Technology
Type of Journal: With a review process (peer review)
Access scheme: Publicly accessible
License: Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες
URI: http://hdl.handle.net/11400/6069
Appears in Collections:Τόμος 08, τεύχος 3 (2013)

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