Please use this identifier to cite or link to this item: http://hdl.handle.net/11400/8092
Title: On the design of efficient modular adders
Authors: Βέργος, Χαρίδημος Τ.
Ευσταθίου, Κωνσταντίνος Η.
Item type: Journal article
Keywords: Computer arithmetic;Αριθμητική υπολογιστών;Modular adders;Residue number system;Υπόλοιπο σύστημα αριθμού;VLSI design;Σχεδιασμό VLSI
Subjects: Computer science
Computer programming
Πληροφορική
Προγραμματισμός
Issue Date: 17-Mar-2015
Oct-2005
Date of availability: 17-Mar-2015
Abstract: Modular adders are met in various applications of computer systems. In this paper, we investigate a new architecture for their design that utilizes a carry save adder stage and two binary adders that operate in parallel. Realizations in static CMOS reveal that the introduced architecture leads to modular adder implementations that offer significant savings in delay and power consumption over implementations based on previously proposed architectures. In parallel, the proposed architecture offers significantly smaller implementation area for small operand widths.
Language: English
Journal: Journal of Circuits, Systems, and Computers
Type of Journal: With a review process (peer review)
Access scheme: Publicly accessible
License: Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες
URI: http://hdl.handle.net/11400/8092
Appears in Collections:Αποτελέσματα ερευνητικών έργων

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