Please use this identifier to cite or link to this item: http://hdl.handle.net/11400/8098
Title: Design of efficient modulo 2n + 1 multipliers
Authors: Βέργος, Χαρίδημος Τ.
Ευσταθίου, Κωνσταντίνος Η.
Item type: Journal article
Keywords: Logic design--Computer programs;Adders;Αθροιστές;Λογική σχεδίαση;Residue number systems;Multiplying circuits;Κυκλώματα πολλαπλασιασμού
Subjects: Computer science
Computer programming
Πληροφορική
Προγραμματισμός
Issue Date: 17-Mar-2015
Jan-2007
Date of availability: 17-Mar-2015
Abstract: A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions.
Language: English
Journal: IET Computers & Digital Techniques
Type of Journal: With a review process (peer review)
Access scheme: Publicly accessible
License: Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες
URI: http://hdl.handle.net/11400/8098
Appears in Collections:Αποτελέσματα ερευνητικών έργων

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